In systems which permit multiprocessing, including systems that permit multithreading, multiple threads or software processes may share a common address space. Accordingly, in some cases, identical virtual addresses may translate into identical physical addresses. For instance, to prevent mistakes in accessing high-speed storage, such as a cache memory, the data may be stored according to physical addresses instead of virtual addresses used by the software processes. A translation lookaside buffer (TLB) is a data structure that may be used to improve virtual address translation speed. For example, a processor may use a TLB to map virtual and physical address spaces. The TLB is typically implemented as content-addressable memory in which a virtual address serves as a search key and a corresponding physical address is a search result. If a requested address is present in the TLB, the search yields a match quickly (a TLB hit), and the retrieved physical address can be used to access memory. On the other hand, if the requested address is not in the TLB (a TLB miss), a process called a page walk may be performed to read the contents of a page table and determine the physical address. After the physical address is determined, the virtual-address-to-physical-address mapping may be entered into the TLB.
If a cache is accessed by multiple logical processors or multiple threads of execution, the size of the TLB may be increased to allow storage of virtual address translations for each logical processor or thread. Unfortunately, the time required to perform a virtual address translation increases with the size of the TLB, thereby reducing access speed and overall system performance.